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1 for more information www.linear.com/ltc4317 typical a pplica t ion fea t ures descrip t ion dual i 2 c/smbus address translator the lt c ? 4317 enables the hardwired address of one or more i 2 c or smbus slave device to be translated to a different ad - dress. this allows slaves with the same hardwired address to coexist on the same bus. only discrete resistors are needed to select the new address and no software programming is required. up to 127 different address translations are available. the ltc4317 incorporates a pass-through mode which dis - ables the address translation and allows general call address - ing by the master. the ltc4317 is designed to automatically recover from abnormal bus conditions like bus stuck low or premature stop bits. the ltc4317 has two output channels for two different sets of slaves. the input channels are tied together to a com - mon set of pins to reduce the pin count and package size. part number number of input channels number of output channels ltc4316 1 1 ltc4317 1 2 ltc4318 2 2 a pplica t ions n allows multiple slaves with the same address to coexist on the same bus n resistor configurable address translation n no software programming required n compatible with smbus, i 2 c and i 2 c fast mode n pass-through mode allows general call addressing n 4kv hbm esd ruggedness n level translation for 2.5v, 3.3v and 5v buses n stuck bus timeout n prevents sda and scl corruption during live board insertion and removal n support bus hot swap n 16-lead dfn 5mm 3mm package n i 2 c, smbus address expansion n address translation n servers n telecom l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6356140, 6650174, 7032051, 7478286. patent pending. 4317 ta01b translation byte sdaout1 sclin sdain address bits start a6 a5 a4 a3 a2 a1 a0 0 1 1 0 1 0 0 = 0x34 0 0 0 0 0 1 0 = 0x02 0 0 0 0 1 1 0 1 1 0 = 0x36 r/w bit ack bit scl sda 4317 ta01a 3.3v 845k 61.9k 3.3v 3.3v master sclout1 sdaout1 ready1 sclin sdain enable1 sends address 0x34 scl sda 5v slave# 1 address 0x36 receives address 0x36 translates by 0x04 translates by 0x02 xorl1 xorl2 ltc4317 v cc gnd enable2 ready2 93.1k sclout2 sdaout2 xorh2 xorh1 scl sda 5v receives address 0x30 slave# 2 address 0x36 lt c4317 4317fa
2 for more information www.linear.com/ltc4317 a bsolu t e maxi m u m r a t ings o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4317cdhc#pbf ltc4317cdhc#trpbf 4317 16-lead (5mm 3mm) plastic dfn 0c to 70c ltc4317idhc#pbf ltc4317idhc#trpbf 4317 16-lead (5mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. p in c on f igura t ion input supply voltage v cc ............................. C 0.3 v to 6v input voltages enablen ...................................................... C 0. 3v to 6v xorln, xorhn ................................ C 0. 3v to v cc + 0.3v output voltages readyn ....................................................... C 0. 3v to 6v output currents readyn, sdaoutn ................................................ 5 0ma input/output voltages sclin, scloutn, sdain, sdaoutn ............ C 0. 3v to 6v operating temperature range lt c 4317 c ................................................ 0c to 7 0c lt c 4317 i ............................................. C 40 c to 85c storage temperature range .................. C 65 c to 150c (notes 1, 2) 16 15 14 13 12 11 10 9 17 gnd 1 2 3 4 5 6 7 8 sclout2 sclin sclout1 sdaout1 sdain sdaout2 ready1 ready2 gnd enable2 xorh2 xorl2 xorh1 xorl1 v cc enable1 top view dhc package 16-lead (5mm 3mm) plastic dfn t jmax = 150c, ja = 42c/w exposed pad (pin 17) is gnd, pcb connection optional lt c4317 4317fa
3 for more information www.linear.com/ltc4317 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v, unless otherwise specified. symbol parameter conditions min typ max units supply v cc input supply range l 2.25 5.5 v i cc input supply current enable = 3.3v, sclin = sdain = 0v l 0.8 2 ma enable = 0v, sclin = sdain = 0v l 350 800 a v cc(uvlo) v cc supply undervoltage lockout v cc rising l 1.9 2.1 2.2 v v cc(hyst) v cc supply undervoltage lockout hysteresis 100 mv enable and ready v enable(th) enable threshold voltage enable rising l 1 1.4 1.8 v v enable(hyst) enable hysteresis 50 mv i enable(leak) enable input current l 1 a v ready(ol) ready output low voltage i = 3ma l 0.4 v i ready(oh) ready off leakage current v cc = v ready = 5.5v l 5 a sclin, sdain, sclout, sdaout v scl,sda(th) threshold voltage sda, scl pins rising l 1.5 1.8 2.0 v v scl,sda(hyst) hysteresis 50 mv i scl,sda(leak) leakage current sda, scl pins = 5.5v, 0v , v cc = 5.5v, 0v l 10 a i scl,sda(leak-inout) input to output leakage current sdain, sclin pins = 5.5v, v cc = 5.5v, sdaout, sclout pins = 4.5v l 10 a c scl,sda pin capacitance note 3 l 10 pf v scl,sda(pre) precharge voltage l 0.8 1 1.2 v v sdaout(ol) sdaout output low voltage i = 4ma l 0.4 v r ds(on) pass switch on resistance v cc = 2.25v, sclin = sdain = 0.4v v cc = 3.3v, sclin = sdain = 0.4v v cc = 5v, sclin = sdain = 0.4v l l l 3 2.2 1.8 12 8 6 xorh, xorl i xorh/xorl xorh and xorl input current l 100 na i 2 c interface timing f scl(max) maximum sclin clock frequency note 3 l 400 khz t pdhl(sdaoutn) sdaout fall delay c = 100pf, r pullup = 10k l 170 300 ns t f(sdaoutn) sdaout fall time c = 100pf, r pullup = 10k l 20 60 300 ns t timeout stuck bus timeout sclin held low or high l 25 30 35 ms t idle bus idle time l 80 120 160 s t glitch sclin and sdain glitch filter l 50 100 ns note 2: all currents into pins are positive and all voltages are referenced to gnd unless otherwise indicated. note 3: guaranteed by design and not tested. lt c4317 4317fa
4 for more information www.linear.com/ltc4317 typical p er f or m ance c harac t eris t ics pass switch on resistance vs temperature ready output low voltage vs current sdaout fall delay vs temperature supply current vs temperature standby supply current vs temperature pass switch on resistance vs v cc t a = 25c, v cc = 3.3v unless otherwise noted. ti m ing diagra m 4317 ec sdaout sdain 50% t pdhl(sdaout) t f(sdaout) 70% 30% 50% temperature (c) ?50 i cc (ma) 1.0 0.9 0.8 0.7 0.6 0 50 ?25 25 75 4317 g01 100 enable = v cc v cc = 3.3v v cc = 5v v cc = 2.25v temperature (c) ?50 i cc (a) 800 700 500 300 600 400 200 100 0 0 50 ?25 25 75 4317 g02 100 enable = 0v v cc (v) 2.0 r ds(on) () 6 5 3 1 4 2 0 3.0 4.0 2.5 3.5 4.5 4317 g03 5.0 t a = ?40c t a = 85c t a = 25c sdain = sclin = 0.4v temperature (c) ?50 r ds(on) () 6 5 3 1 4 2 0 0 50 ?25 25 75 4317 g04 100 v cc = 5v v cc = 2.25v v cc = 3.3v sdain = sclin = 0.4v i ready (ma) 0 v ready(ol) (mv) 100 80 40 60 20 0 2 64 8 4317 g05 10 t a = ?40c t a = 85c v cc = 3.3v t a = 25c temperature (c) ?50 t pdhl(sdaout) (ns) 240 200 220 160 180 140 100 120 0 50 ?25 25 75 4317 g06 100 v cc = 3.3v c = 100pf lt c4317 4317fa
5 for more information www.linear.com/ltc4317 typical p er f or m ance c harac t eris t ics sdaout fall delay vs bus capacitance sdaout fall time vs temperature sdaout fall time vs bus capacitance t a = 25c, v cc = 3.3v unless otherwise noted. p in func t ions xorl1/xorl2: translator xor lower nibble configura - tion input. the dc voltage at this pin configures the lower 4- bit nibble of the address translation byte. tie the pin to an external resistive divider connected between v cc and gnd to set the desired dc voltage. xorh1/xorh2: translator xor upper nibble configura - tion input. the dc voltage at this pin configures the upper 3-bit nibble of the address translation byte. tie the pin to an external resistive divider connected between v cc and gnd to set the desired dc voltage. connect this pin to v cc to activate pass-through mode. see application informa - tion section for more details. enab le1/enable2: enable input. if enable pin is low, the address translation is disabled, sdain is disconnected from sdaout, and sclin is disconnected from sclout. a low to high transition on enable restarts the configura - tion of the address translation byte and also enables the address translation. connect to v cc if unused. exposed pad : exposed pad may be left open or connected to device gnd. gnd: device ground. ready1/ready2: ready status output. this is an open drain output to indicate that the device is ready for address translation. the pin releases high when the ltc4317 has completed configuration of the address translation byte, sdain is connected to sdaout and sclin is connected to sclout. connect a pull-up resistor, typically 10k , from this pin to the bus pull-up supply. leave open or tie to gnd if unused. sclin: input bus clock input and output. connect this pin to the scl line on the master side. an external pull-up resistor or current source is required. sclout1/sclout2: output bus clock input and output. connect this pin to the scl line on the slave side. an external pull-up resistor or current source is required. connect to v cc through a pull-up resistor if unused. sdain: input bus data input and output. connect this pin to the sda line on the master side. an external pull-up resistor or current source is required. sdaout1/sdaout2: output bus data input and output. connect this pin to the sda line on the slave side. an external pull-up resistor or current source is required. connect to v cc through a pull-up resistor if unused. v cc : power supply input (2.25v to 5.5v). if the supply voltages for the input and output buses are different, con - nect this pin to the lower supply. if the input and output supplies have the same nominal value and with tolerance less than or equal to 10%, connect v cc to either supply. bypass with at least 0.1f to gnd. c bus (pf) 0 t pdhl(sdaout) (ns) 300 250 275 150 200 175 225 125 100 200 600 400 800 4317 g07 1000 v cc = 3.3v v cc = 5v v cc = 2.25v temperature (c) ?50 t f(sdaout) (ns) 120 100 60 80 40 20 0 50 ?25 25 75 4317 g08 100 c = 100pf v cc = 5v v cc = 2.25v v cc = 3.3v c bus (pf) 0 t f(sdaout) (ns) 120 100 60 80 40 20 200 600 400 800 4317 g09 1000 v cc = 5v v cc = 2.25v v cc = 3.3v lt c4317 4317fa
6 for more information www.linear.com/ltc4317 b lock diagra m 4317 bd i 2 c hot swap logic 7-bit address translation byte gnd control logic v cc /2 cmp6 cmp5 precharge 1.4v n4 1v 200k precharge 1v ready1 sdaout1 sclout1 xorl1 xorh1 sdain sclin sdaout2 sclout2 v cc ? + n3 ? + cmp3 1.8v ? + 1.8v cmp1 ? + i 2 c hot swap logic cmp4 1.8v ? + glitch filter 1.8v cmp2 ? + glitch filter xor n1 n2 200k precharge precharge precharge 1v 200k 1v 200k enable1 ready2 xorl2 xorh2 enable2 lt c4317 4317fa
7 for more information www.linear.com/ltc4317 o pera t ion figure 1. basic functions of the ltc4317 4317 f01 v cc1 master sclout sdaout sclin sdain v cc2 slave #1 ltc4317 slave #2 7-bit address translation byte shift register 0000010 enable address translation n3 1.8v cmp2 ? + xor n1 n2 in most conditions, n1 and n2 stay on so that the input and output buses are connected. translation starts when the master issues a start bit (sdain goes low while sclin is high). the ltc4317 turns off n2 to disconnect sdain from sdaout. as the master sends the address byte, the ltc4317 translates the incoming address at the sdain pin to a new address at the sdaout pin by xoring each incoming bit with a user-configurable translation byte, one bit at a time. n3 turns on and off to send out the new address to the sdaout?pin. once all 7 bits of the address are processed, the ltc4317 turns on n2 again to reconnect sdain to sdaout. the master then transmits the r/w bit directly to the slave. if the new, translated address on sdaout matches the slaves address, the slave pulls sdaout low to acknowledge (ack bit). n2 remains on and the rest of the data bytes are transmitted unmodified between the master and slave. the address translation process restarts when the master issues a new start bit. the ltc4317 is an i 2 c/smbus address translator. it bridges two segments of an i 2 c bus, reading incoming addresses on the master side and retransmitting them to the slave side with the 7-bit i 2 c addresses translated in real time. this allows multiple i 2 c devices with the same address to be connected to the same bus without interference. the translated addresses are configured with external resistors, and no extra software is required. an enable pin allows bus segments to be enabled and disabled, and the ltc4317 allows hot swapping isolated bus segments together. figure 1 shows an i 2 c master connected to the input bus of the ltc4317 (sclin and sdain). the slave devices requiring address translation are connected to the output bus of the ltc4317 (sclout and sdaout). any other slave devices that do not require address translation are placed together with the master on the input bus of the ltc4317 . two switches (n1 and n2) inside the ltc4317 connect the input bus to the output bus. n1 connects sclin to sclout while n2 connects sdain to sdaout. lt c4317 4317fa
8 for more information www.linear.com/ltc4317 o pera t ion table 1. description binary address 7-bit hex address without r/w 8-bit hex address with r/w = 0 a6 a5 a4 a3 a2 a1 a0 r/w input address from sdain 0 0 1 1 0 1 0 0 0x1a 0x34 translation byte 0 0 0 0 0 0 1 0 0x01 0x02 output address to sdaout 0 0 1 1 0 1 1 0 0x1b 0x36 figure 2. basic address translation waveforms translation byte sdaout sclin sdain address bits start a6 a5 a4 a3 a2 a1 a0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 1 0 4317 f02 n2 gate n2 on n2 on n2 off r/w bit ack bit = 0x34 = 0x02 = 0x36 figure 2 shows typical waveforms for the circuit on the front page. in this example, the master transmits address 0x 34 while the slave is configured to respond to address 0x36. the resistive dividers at the xorl and xorh pins are configured to generate an address translation byte of 0x02. note that in this example, the 8-bit hexadecimal address format (with r/w = 0) is used. 7-bit addresses are also commonly found in i 2 c device documentation. make sure to use the correct format when calculating the address translation byte. table 1 shows examples of both formats. lt c4317 4317fa
9 for more information www.linear.com/ltc4317 figure 4. two slaves sharing one channel of ltc4317 figure 3. two independent address translation o pera t ion scl sda 4317 f03 master sclout1 sdaout1 sclin sdain scl sda slave #1 ltc4317 sclout2 sdaout2 scl sda slave #3 scl sda slave #2 slave #1 input address 0x32 translation byte 0x06 hardwired address 0x34 slave #3 input address 0x36 translation byte 0x02 hardwired address 0x34 hardwired address 0x34 00110010 00000110 00110100 00110110 00000010 00110100 scl sda 4317 f04 master scl sda slave #2 sclout sdaout sclin sdain scl sda slave #1 ltc4317 scl sda slave #3 hardwired address 0x34 translation byte 0x02 slave #1 input address 0x36 slave #3 input address 0x32 hardwired address 0x34 hardwired address 0x30 00110110 00000010 00110100 00110010 00000010 00110000 system configurations there are several ways that individual slaves or banks of slaves can be connected to an ltc4317. in figure 3, each slave is paired with one channel of the ltc4317 . this configuration allows for maximum flexibility in allocating the bus addresses. both read and write operations and all protocols supported by the ltc4317 are allowed. figure?4 shows two slaves with different hardwired addresses translated to two different addresses using one channel of the ltc4317 and a common translation byte. a program is available to help the user visualize an i 2 c bus with the ltc4317; this program can be found in the following link: www.linear .com/translatortool setting the translation byte when the ltc4317 is first powered up or any time a rising edge is detected on the enable pin, the ltc4317 reads the voltages at the xorh and xorl pins to determine the 7-bit translation byte. these voltages are referenced to v cc so a resistive divider at each of these pins is the most convenient way to set the voltages. the required transla - tion byte can be determined by taking the bitwise xor of the slave s original address and the desired input address. the voltages at the xorh and xorl pins configure the translation byte. the xorl voltage configures the lower?4 translation bits (excluding the r/w bit), while the xorh voltage configures the upper 3 translation bits. tables 2 and 3 show the recommended resistive divider values. r lt and r lb are the top and bottom resistors connected to xorl, while r ht and r hb are the top and bottom resistors connected to xorh (figure 5). use 1% tolerance resistors for r lt , r lb , r ht and r hb . figure 5. address translation byte configuration resistors 4317 f05 v cc r ht r lt xorl xorh ltc4317 v cc r hb r lb lt c4317 4317fa
10 for more information www.linear.com/ltc4317 o pera t ion table 2. setting the resistive divider at xorl lower 4-bit of translation byte v xorl /v cc recommended r lt [k] recommended r lb [k] a3 a2 a1 a0 0 0 0 0 0.03125 open short 0 0 0 1 0.09375 0.015 976 102 0 0 1 0 0.15625 0.015 976 182 0 0 1 1 0.21875 0.015 1000 280 0 1 0 0 0.28125 0.015 1000 392 0 1 0 1 0.34375 0.015 1000 523 0 1 1 0 0.40625 0.015 1000 681 0 1 1 1 0.46875 0.015 1000 887 1 0 0 0 0.53125 0.015 887 1000 1 0 0 1 0.59375 0.015 681 1000 1 0 1 0 0.65625 0.015 523 1000 1 0 1 1 0.71875 0.015 392 1000 1 1 0 0 0.78125 0.015 280 1000 1 1 0 1 0.84375 0.015 182 976 1 1 1 0 0.90625 0.015 102 976 1 1 1 1 0.96875 short open table 3. setting the resistive divider at xorh upper 3-bit of translation byte v xorh /v cc recommended r ht [k] recommended r hb [k] a6 a5 a4 0 0 0 0.03125 open short 0 0 1 0.09375 0.015 976 102 0 1 0 0.15625 0.015 976 182 0 1 1 0.21875 0.015 1000 280 1 0 0 0.28125 0.015 1000 392 1 0 1 0.34375 0.015 1000 523 1 1 0 0.40625 0.015 1000 681 1 1 1 0.46875 0.015 1000 887 for example, if r lt = 976k , r lb = 102k , r ht = 1000k , and r hb = 280k , the lower 4 translation bits are 0001b and the upper 3 bits are 011b. the 8-bit hexadecimal address translation byte is obtained by adding a 0 as the lsb, which gives 0110 0010b or 0x62. if the configuration voltages at xorl and xorh pins are the same, they can be tied together and connected to a single resistive divider. alternatively, three resistors can be used to configure the xorl and xorh pins (figure 6). use the following procedure to calculate the value of the three resistors: figure 6. address translation byte configuration using three resistors 4317 f06 v cc r a1 xorh ltc4317 v cc xorl r a3 r a2 first choose a total resistance value r total r a3 = r total ? (v xorh /v cc ) r a2 = (r total ? v xorl /v cc ) C ra3 r a1 = r total C r a3 C r a2 use 1% tolerance resistors for r a1 , r a2 and r a3 . once the xorl and xorh pins are read, the ltc4317 turns on switches n1 and n2, connecting the input and output, and the ready pin goes high to indicate that the ltc4317 is ready to start address translation. the address translation byte can be changed during operation by changing the xorh and xorl voltages and toggling the enable pin (high-low-high). this triggers the ltc4317 to re-read the xorl and xorh voltages. enable/uvlo if the enable pin is driven below v enable(th) or if v cc is below the uvlo threshold, the ltc4317 shuts down. the internal shift register storing the address translation byte is cleared, address translation is disabled, switches n1, n2 and n3 are off, the ready pin is pulled low and the quiescent current drops to 350a. lt c4317 4317fa
11 for more information www.linear.com/ltc4317 o pera t ion precharge and hot swap when the ltc4317 is first powered on, switches n1 and n2 are initially off. this allows a ltc4317 and its con - nected slaves to be hot swapped onto an active i 2 c bus. internal precharge circuitry initially sets the bus lines to 1v through a 200k resistor, minimizing disturbance to an active bus when the ltc4317 is connected. the ltc4317 keeps n1 and n2 off until enable goes high, the xorl/ xorh pins are read, and both sides of the i 2 c bus are idle (indicated either by a stop bit or all bus pins high for longer than 120s). once these conditions are met, n1 and n2 turn on, and the ready pin goes high to indicate that the ltc4317 is ready to start address translation. pass-through mode if the master wants to communicate with the slave us - ing the general call address, it can temporarily disable address translation by pulling xorh high. this disables address translation and keeps n1 and n2 on regardless of the activity on the buses. any translation that may be in progress is stopped immediately when xorh goes high. extra transitions on sdaout in an i 2 c/smbus system, the master changes the state of the sda line when scl is low. the ltc4317 also advances the address translation byte shift register when the sclin is low. the translation byte transitions occur approximately 100ns after the falling edge of sclin. if the sdain tran - sitions sent by the master do not coincide exactly with the ltc4317 address translation bit transitions, an extra transition on sdaout may appear (figure? 7). these extra sda transitions are like glitches similar to those occurring during normal acknowledge bit transitions and do not pose problems in the system because devices on the bus latch sda data only when scl is high. level translation and supply voltage matching the ltc4317 can operate with different supply voltages on the input and output bus, and it will level shift the voltages on the sclin, sdain, sclout, and sdaout pins to match the supply voltage at each side. v cc must be powered from the lower of the two supply voltages for level shifting to operate correctly. for example, if the input bus is powered by a 5v supply and the output bus is powered by a 3.3v supply, the ltc4317 vcc pin must be connected to the 3.3v supply as shown in figure 8. if the ltc4317 supply pin is connected to the higher bus supply, current may flow through the switches n1 and n2 to the bus with lower supply. if the voltage difference figure 7. extra transitions on sdaout while scl is low translation byte sdaout sclin sdain glitch 0 1 0 1 0 1 1 0 0 0 1 1 4317 f07 n2 gate n2 off address bits glitch figure 8. a 5v to 3.3v level translation application 4317 f08 5v master sclout sdaout sclin sdain 3.3v slave #1 ltc4317 v cc is less than 1v, this current is limited to less than 10a. this allows the input and output buses to be connected to nominally identical supplies that may have up 10% tolerance, and the ltc4317 v cc pin can be connected to either supply. extra start and stop bits during normal operation, an i 2 c master should not issue a start or stop bit within a data byte. i 2 c slave behavior when such a command is received can be unpredictable. the ltc4317 will recover automatically when an unex - pected start or stop is received during the address byte ; however, depending on the state of the translating bits, it may convert st art bits to stop bits and vice versa, causing unexpected slave behavior. lt c4317 4317fa
12 for more information www.linear.com/ltc4317 o pera t ion if a start bit is received during the address byte when the active translating bit is a "1", the slave device will see a stop bit. this will typically reset the slave and cause it to miss the remainder of the transmission. if the start bit is received while the active translating bit is a "0", the start passes through the ltc4317 unchanged. the slave will react in the same way it would if the ltc4317 was not present, and will typically reset when the master next issues a stop bit. in both cases, the ltc4317 automati - cally resets at the next stop bit and the next message will be transmitted normally. if a stop bit is received during the address byte, the ltc4317 will abort the address translation and ensure that a stop bit is issued at sdaout to reset the slave. if the active translating bit is a "0" when the stop arrives, it is not modified, and the slave will see the stop and typically reset. if the active translating bit is a "1" when the stop arrives, the slave device will see a start bit. this might leave the slave in an indeterminate state, so the ltc4317 briefly disconnects the slave from the master, adds a short delay, and then generates a stop bit at the sdaout pin (figure 9). it then reconnects the busses and waits for a start bit to begin the next transmission. again, in both cases, the ltc4317 automatically resets and the next message will be transmitted normally. stuck bus timeout during the address translation, if sclin stays low or high for more than 30ms without any transitions, the ltc4317 will abort the address translation and reconnect sdain to sdaout. it will then wait for a start bit to start a new address translation. this prevents any bus stuck low/ high conditions from permanently disconnecting sdain from?sdaout. supported protocols the ltc4317 is designed to support most i 2 c and smbus message protocols. the only exceptions are protocols that use pre-assigned addresses on the slave side of the bus. supported i 2 c and smbus protocols: send/receive byte write byte/word read byte/word process call block write/read block write-block read process call extended read and write commands general call (i 2 c only) start byte (i 2 c only) pmbus (without pec) unsupported i 2 c protocols: 10-bit addressing device id ultra fast-mode i 2 c bus protocol unsupported smbus protocols: smbus host notify address resolution protocol (arp) parity error code (pec) alert response address (ara) pmbus (with pec) figure 9. stop bit within address byte when address translation byte is 1 translation byte sdaout sclin sdain n2 gate n2 off n2 off n2 on address bit becomes stop bit stop bit start bit 1 4317 f09 n1 gate n1 on n1 on n1 off start bit stop bit start bit lt c4317 4317fa
13 for more information www.linear.com/ltc4317 typical a pplica t ions figure 10. ltc4317 with address translation byte of 0x02 and 0x04 4317 f10 v cc 845k 61.9k v cc v cc sclout1 sdaout1 enable1 scl1 sda1 gnd v cc sclin sdain ready1 to master scl to master sda plug-in card 1 motherboard connector 1 input address 0x32 to slave #1 hardwired address 0x30 xorl1 xorl2 xorh1 xorh2 ltc4317 v cc ready2 93.1k v cc 10k 10k 10k 10k 10k10k 10k sclout2 sdaout2 enable2 scl2 sda2 gnd v cc plug-in card 2 motherboard connector 2 input address 0x34 to slave #2 hardwired address 0x30 v cc 10k 10k 10k lt c4317 4317fa
14 for more information www.linear.com/ltc4317 p ackage descrip t ion please refer to http://www.linear.com/product/ltc4317#packaging for the most recent package drawings. 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05 dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706 rev ?) lt c4317 4317fa
15 for more information www.linear.com/ltc4317 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 10/15 minor edits 4, 5 lt c4317 4317fa
16 for more information www.linear.com/ltc4317 ? linear technology corporation 2015 lt 1015, ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4317 r ela t e d p ar t s typical a pplica t ion part number description comments LTC4300A-1/ ltc4300a-2/ ltc4300a-3 hot swappable 2-wire bus buffers LTC4300A-1: bus buffer with ready and enable ltc4300a-2: dual supply buffer with acc ltc4300a-3: dual supply buffer and enable lt c4302-1/ ltc4302-2 addressable 2-wire bus buffer address expansion, gpio, software controlled ltc4303/ ltc4304 hot swappable 2-wire bus buffer with stuck bus recover y provides automatic clocking to free stuck i 2 c busses ltc4305/ ltc4306 2- or 4-channel, 2-wire bus multiplexers with capacitance buffering two or four software selectable downstream busses, stuck bus disconnect, rise time accelerators, fault reporting, 10kv hbm esd ltc4307 low offset, hot swappable 2-wire bus buffer with stuck bus recovery 60mv buffer offset, 30ms stuck bus disconnect and recovery, rise time accelerators, 5kv hbm esd ltc4307-1 high definition multimedia interface (hdmi) level shifting 2-wire bus buffer 60mv buffer offset, 3.3v to 5v level shifting, 5kv hbm esd ltc4308 low voltage, level shifting hot swappable 2-wire bus buffer with stuck bus recovery bus buffer with 1v precharge, enable and ready, 0.9v to 5.5v level translation, 30ms stuck bus disconnect and recovery, output side rise time accelerators, 6kv hbm esd ltc4309 low offset hot swappable 2-wire bus buffer with stuck bus recovery 60mv buffer offset, 30ms stuck bus disconnect and recovery, rise time accelerators, 5kv hbm esd, 1.8v to 5.5v level translation ltc4310-1/ ltc4310-2 hot swappable i 2 c isolators bidirectional i 2 c communication between two isolated busses, ltc4310-1: 100khz bus, ltc4310-2: 400khz bus ltc4311 hot swappable i 2 c/smbus accelerator rise time acceleration with enable, 8kv hbm esd ltc4312/ ltc4314 2- or 4-channel, hardware selectable 2-wire bus multiplexers with capacitance buffering two or four pin selectable downstream busses, v il up to 0.3v ? v cc , rise time accelerators, 45ms stuck bus disconnect and recovery, 4kv hbm esd ltc4313-1/ ltc4313-2/ ltc4313-3 high noise margin 2-wire bus buffers v il = 0.3v ? v cc , rise time accelerators, stuck bus disconnect and recovery, 1v precharge, 4kv hbm esd figure 11. comparison between ltc4316/ltc4317/ltc4318 4317 f11 sclout sdaout ready sclout sdaout ready v cc sclin sdain xorh xorl enable gnd sclin sdain xorh xorl enable single ltc4316 sclout1 sdaout1 ready1 sclout sdaout ready v cc sclin sdain xorh1 xorl1 enable1 sclin sdain xorh xorl enable ?y? connected dual ltc4317 sclout2 sdaout2 ready2 sclout sdaout ready sclin sdain xorh xorl enable channel2 channel1 sclout1 sdaout1 ready1 sclout sdaout ready v cc sclin1 sdain1 xorh1 xorl1 enable1 sclin sdain xorh xorl enable dual ltc4318 sclout2 sdaout2 ready2 sclout sdaout ready sclin2 sdain2 xorh2 xorl2 enable2 gnd sclin sdain xorh xorl enable channel2 channel1 xorh2 xorl2 enable2 gnd lt c4317 4317fa

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